TRF7970A
www.ti.com
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
5.3
Electrical Characteristics
TYP operating conditions are T A = 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All building blocks disabled, including supply-
I PD1
Supply current in Power Down Mode 1
voltage regulators; measured after 500-ms
0.5
5
μA
settling time (EN = 0, EN2 = 0)
I PD2
I STBY
I ON1
I ON2
I ON3
Supply current in Power Down Mode 2
(Sleep Mode)
Supply current in stand-by mode
Supply current without antenna driver
current
Supply current – TX (half power)
Supply current – TX (full power)
The SYS_CLK generator and V DD_X remain
active to support external circuitry; measured
after 100-ms settling time (EN = 0, EN2 = 1)
Oscillator running, supply-voltage regulators in
low-consumption mode (EN = 1, EN2 = x)
Oscillator, regulators, RX and AGC active, TX
is off
Oscillator, regulators, RX and AGC and TX
active, P OUT = 100 mW
Oscillator, regulators, RX and AGC and TX
active, P OUT = 200 mW
120
1.9
10.5
70
130
200
3.5
14
78
150
μA
mA
mA
mA
mA
V POR
V BG
V DD_A
V DD_X
I VDD_Xmax
Power-on reset voltage
Bandgap voltage (pin 11)
Regulated output voltage for analog
circuitry (pin 1)
Regulated supply for external circuitry
Maximum output current of V DD_X
Input voltage at V IN
Internal analog reference voltage
V IN = 5 V
Output voltage pin 32, V IN = 5 V
Output current pin 32, V IN = 5 V
1.4
1.5
3.1
3.1
2
1.6
3.4
3.4
2.6
1.7
3.8
3.8
20
V
V
V
V
mA
R RFOUT
Antenna driver output resistance
(1)
Half-power mode, V IN = 2.7 V to 5.5 V
Full-power mode, V IN = 2.7 V to 5.5 V
8
4
12
6
Ω
R RFIN
V RF_INmax
V RF_INmin
RX_IN1 and RX_IN2 input resistance
Maximum RF input voltage at RX_IN1 and
RX_IN2
Minimum RF input voltage at RX_IN1 and
RX_IN2 (input sensitivity) (2)
V RF_INmax should not exceed V IN
f SUBCARRIER = 424 kHz
f SUBCARRIER = 848 kHz
4
10
3.5
1.4
2.1
20
2.5
3
k Ω
V pp
mV pp
f SYS_CLK
f C
t CRYSTAL
f D_CLKmax
R OUT
R SYS_CLK
SYS_CLK frequency
Carrier frequency
Crystal run-in time
Maximum DATA_CLK frequency (4)
Output resistance I/O_0 to I/O_7
Output resistance R SYS_CLK
In power mode 2, EN = 0, EN2 = 1
Defined by external crystal
Time until oscillator stable bit is set (register
0x0F) (3)
Depends on capacitive load on the I/O lines,
recommendation is 2 MHz (4)
25
2
60
13.56
3
8
500
200
120
10
800
400
kHz
MHz
ms
MHz
Ω
Ω
(1)
(2)
(3)
(4)
Antenna driver output resistance
Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.
Depends on the crystal parameters and components
Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω (12-ns time constant when 30-pF load used).
Copyright ? 2011–2014, Texas Instruments Incorporated
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Specifications
9
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